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| CXD2411AR Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office. Description The CXD2411AR is a timing signal generator for color LCD panel drivers. Features * Generates the LCX005BK/BKB and LCX009AK/AKB drive pulse. * Supports right/left inverse display. * Supports 16:9 wide display. * Supports CSYNC and Separate SYNC (XHD, XVD) input. * Supports line inversion and field inversion. * AC drive for LCD panel during no signal (NTSC/PAL). * Generates timing signal of external sample-andhold circuit. * AFC circuit supporting static and dynamic fluctuations. Applications * Color LCD viewfinder * Single-panel and three-panel projectors Structure Silicon gate CMOS IC 48 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25C) VSS - 0.5 to +7.0 V * Supply voltage VDD * Input voltage VI VSS - 0.5 to VDD + 0.5 V * Output voltage VO VSS - 0.5 to VDD + 0.5 V * Operating temperature Topr -20 to +85 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 2.7 to 5.5 * Operating temperature Topr -20 to +85 V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95Z14-ST CXD2411AR Block Diagram and Pin Configuration CKO 41 master ck CKI 42 PLL PHASE COMPARATOR XCLR PLNT SLCK 3 2 1 35 XCLP XHD 27 XVD 45 H-SYNC DETECTOR H-SKEW DETECTOR 36 HD HALF-H KILLER 39 RPD PLL-COUNTER 6 VSS 19 VDD TST0 TST1 TST2 7 8 9 V-SYNC SEPERATOR (NOISE SHAPE) 31 VSS 43 VDD 40 VSS TST3 11 TST4 12 TST5 15 TST6 26 TST7 37 TST8 44 46 HP1 47 HP2 48 HP3 38 HP4 10 H-TIMING PULSE GENERATOR RGT 22 HST1 14 HST2 24 HCK1 23 HCK2 32 SH1 33 SH2 EN 17 VD 25 VST 18 VCK1 21 VCK2 20 FLDO 29 SBLK WIDE 5 4 V-TIMING PULSE GENERATOR 34 SH3 30 SH4 PAL PULSE ELIMINATOR FIELD & LINE CONTROLLER 16 CLR 13 SLFR 28 FRP -2- CXD2411AR Pin Description Pin Symbol No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SLCK PLNT XCLR WIDE SBLK VSS TST0 TST1 TST2 RGT TST3 TST4 SLFR HST2 TST5 CLR EN VST VDD VCK2 VCK1 HST1 HCK2 HCK1 VD TST6 XHD FRP FLDO SH4 VSS SH1 SH2 SH3 XCLP HD TST7 I/O I I I I O -- -- -- -- I -- -- I O -- O O O -- O O O O O O -- I O O O -- O O O O O -- Description Switches between LCX005BK (H) and LCX009 (L) Switches between PAL (H) and NTSC (L) Cleared at 0V Switches between 16:9 display (H) and 4:3 display (L) Black signal pulse output (during WIDE MODE) (positive polarity) GND Leave this open. Leave this open. Leave this open. Switches between Normal scan (H) and Reverse scan (L) Leave this open. Leave this open. Switches between field inversion (H) and line inversion (L) H start pulse 2 (positive polarity) Leave this open. CLR pulse output (positive polarity) EN pulse output (negative polarity) V start pulse (positive polarity) Power supply V clock pulse 2 V clock pulse 1 H start pulse 1 (positive polarity) H clock pulse 2 H clock pulse 1 VD pulse output (positive polarity) Leave this open. XHD (negative polarity)/Composite sync (positive polarity) input AC drive timing pulse output Field identification signal output Sample-and-hold pulse (positive polarity) GND Sample-and-hold pulse (positive polarity) Sample-and-hold pulse (positive polarity) Sample-and-hold pulse (positive polarity) Burst position clamp pulse output (negative polarity) HD pulse output (positive polarity) Leave this open. -3- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- H -- -- L -- -- -- -- -- Input pin for open status L L H L -- CXD2411AR Pin Symbol No. 38 39 40 41 42 43 44 45 46 47 48 HP4 RPD VSS CKO CKI VDD TST8 XVD HP1 HP2 HP3 I/O I O -- O I -- -- I I I I Description Switches for the horizontal display position Phase comparator output GND Oscillation cell (output) Oscillation cell (input) Power supply Leave this open. XVD (negative polarity) input Switches for the horizontal display position Switches for the horizontal display position Switches for the horizontal display position Input pin for open status H -- -- -- -- L L L L (H: Pull up, L: Pull down) Note) The CXD2411AR processes CSYNC and Separate SYNC inputs with the same pins. Therefore, care should be given to the following points when using the CXD2411AR. 1) During CSYNC input, the XVD input pin should be set to L or left open. 2) During Separate SYNC input (XHD, XVD), the XVD width specification is from 2H to 10H. -4- CXD2411AR Electrical Characteristics 1. DC characteristics Item Supply voltage Input voltage Input voltage Input voltage Input voltage Input voltage Output voltage Output voltage Output voltage Output voltage Output voltage Output voltage Input leak current Input leak current Input leak current Output leak current Current consumption 2. AC characteristics Item Clock input cycle Cross-point time difference Cross-point time difference Output rise delay Output fall delay Output rise delay Output fall delay HCK1, SH1 delay time difference HCK1, SH1 delay time difference HCK2, SH1 delay time difference HCK2, SH1 delay time difference HCK1 Duty HCK2 Duty Note) n = 1, 2 -5- CKI HCK1, HCK2 VCK1, VCK2 HCKn, VCKn HCKn, VCKn Other than HCKn and VCKn Other than HCKn and VCKn HCK1, SH1 HCK1, SH1 HCK2, SH1 HCK2, SH1 HCK1 HCK2 t t tpr tpf tpr tpf dt1 dt2 dt1 dt2 tH/tH + tL tH/tH + tL CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF CL = 30pF 60 60 60 60 46 46 Applicable pins Symbol Conditions Symbol VDD VIH VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL IL IIL IIH ILZ IDD TTL input cell (5V 10%) TTL input cell (3.0V 10%) TTL input cell CMOS input cell CMOS input cell IOH = -4mA (HCKn, VCKn) IOL = 8mA (HCKn, VCKn) IOH = -3mA (CKO, CKI) IOL = 3mA (CKO, CKI) IOH = -2mA (other than the above) IOL = 4mA (other than the above) Normal input pin With pull-up resistor With pull-down resistor RPDn, FPDn (at high impedance state) VDD = 5.0V -10 -12 12 -40 25 -100 100 VDD - 0.8 0.4 10 -240 240 40 VDD/2 VDD/2 VDD - 0.8 0.4 0.7VDD 0.3VDD Conditions (Temperature = 25C, VSS = 0V) Min. 2.7 2.2 1.8 0.8 Typ. Max. 5.5 Unit V V V V V V V V V V V V A A A A mA (VDD = 2.7 to 5.5V) Min. Typ. Max. Unit 60 10 10 30 25 40 22 85 95 85 95 52 52 ns ns ns ns ns ns ns ns ns ns ns % % CXD2411AR Timing Definition VDD CKI 0V VDD Output 0V tpr VDD Output 0V tpf VDD VCK1 (HCK1) 50% 50% 0V VDD VCK2 (HCK2) 50% 50% 0V t t t CKI t tH - tL = 2 (t - t1) tH = t - t1 + t2 tL = t - t2 + t1 tH - tL = 2 (t2 - t1) HCK1 (HCK2) t1 50% 50% 50% tH t2 tL SH1 50% 50% dt1 dt2 -6- CXD2411AR LCX005BK/BKB and LCX009AK/AKB Color Coding Diagram The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note that the shaded region within the diagram is not displayed. LCX005BK/BKB pixel arrangement HSW1 HSW2 HSW3 HSW174 HSW175 dummy2 to 5 dummy1 dummy2 G B R G B R G B R G B R G B R G B R Photo-shielding area B R G B R G B R G B R G B R G B R G Vline1 Vline2 G B R G B R G B R G B R G B R G B R B R G B R G B R G B R G B R G B R G Vline3 G B R G B R G B R G B R G B R G B R 218 R R R B R G B R G B R G B R G B R G B R G 2 2 222 Display area G B R G B R G B R G B R G B R G B B R G B R G B R G B R G B R G B R G Vline217 Vline218 G B R G B R G B R G B R G B R G B B R G B R G B R G B R G B R G B R G dummy3 dummy4 G B R G B R G B R G B R G B R G B B R G B R G B R G B R G B R G B R G 3 521 537 13 Basic specifications Total horizontal dots Horizontal display dots Total vertical dots Vertical display dots Total dots Display dots -7- : : : : : : 537H 521H 222H 218H 119,214H 113,578H CXD2411AR LCX009AK/AKB pixel arrangement dummy1 to 4 HSW1 HSW2 HSW267 HSW268 dummy5 to 8 dummy1 B R G B R G B R G B R G B R G B R Photo-shielding area dummy2 R G B R G B R G B R G B R G B R G Vline1 Vline2 R B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G Vline3 R B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G 2 R R R B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B Vline224 R G B R G B R G B R G B R G B R G Vline225 dummy3 B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G 14 800 827 13 Basic specifications Total horizontal dots Horizontal display dots Total vertical dots Vertical display dots Total dots Display dots -8- : : : : : : 827H 800H 228H 225H 188,556H 180,000H 1 225 Display area 228 CXD2411AR Description of Mode Selection Switch (SLCK, PLNT, WIDE) SLCK H H H H L L L L PLNT L L H H L L H H WIDE L H L H L H L H MODE LCX005BK/BKB, NTSC, NORMAL LCX005BK/BKB, NTSC, WIDE LCX005BK/BKB, PAL, NORMAL LCX005BK/BKB, PAL, WIDE LCX009AK/AKB, NTSC, NORMAL LCX009AK/AKB, NTSC, WIDE LCX009AK/AKB, PAL, NORMAL LCX009AK/AKB, PAL, WIDE NORMAL (4:3 display), WIDE (16:9 display) SLFR SLFR is the selector switch for the AC drive timing pulse (FRP). This switch selects field inversion when H and line inversion when L. Normally, line inversion (L) is used. The transition point is one clock cycle after the transition point of the VCK1 and VCK2 pulses. FRP 1H inversion (2H cycle) 1H 1H 1H 1H 1F inversion (2F cycle) 1Field 1Field FRP polarity is not specified. -9- CXD2411AR HP1, 2, 3, 4 These are selector switches for the horizontal display position. The HST timing can be set at 2fh intervals in 16 different ways by using the four HST position bits. The picture center is set at internal preset value: HP1/2/3/4: LLLH. However, actually, because there is a difference between the RGB signal and the drive pulse delays, the picture center may not match the design center. In this case, adjust with these switches. The HST timing (from SYNC termination to the rising edge of HST) for even lines is shown below. LCX005BK/BKB (NTSC, PAL) HP4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HP3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HP2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HP1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HST1 (NTSC/PAL) 72fh (6.51/6.56s) 70fh 68fh 66fh 64fh 62fh 60fh 58fh 56fh (5.06/5.11s) 54fh 52fh 50fh 48fh 46fh 44fh 42fh (3.80/3.83s) HST2 (NTSC/PAL) 74.5fh (6.74/6.79s) 72.5fh 70.5fh 68.5fh 66.5fh 64.5fh 62.5fh 60.5fh 58.5fh (5.29/5.33s) 56.5fh 54.5fh 52.5fh 50.5fh 48.5fh 46.5fh 44.5fh (4.02/4.06s) The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above timings. (Refer to the Timing Charts for details.) - 10 - CXD2411AR LCX009AK/AKB (NTSC, PAL) HP4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 HP3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 HP2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HP1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HST1 (NTSC/PAL) 91fh (5.51/5.55s) 89fh 87fh 85fh 83fh 81fh 79fh 77fh 75fh (4.54/4.57s) 73fh 71fh 69fh 67fh 65fh 63fh 61fh (3.69/3.72s) HST2 (NTSC/PAL) 93.5fh (5.66/5.70s) 91.5fh 89.5fh 87.5fh 85.5fh 83.5fh 81.5fh 79.5fh 77.5fh (4.69/4.72s) 75.5fh 73.5fh 71.5fh 69.5fh 67.5fh 65.5fh 63.5fh (3.84/3.87s) The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above timings. (Refer to the Timing Charts for details.) - 11 - CXD2411AR Right/Left Inversion The LCD panel is arranged in a delta pattern, where identical signal line has 1.5-dot offset at adjoining vertical lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd lines and even lines. HCK and SH are also 1.5-bit offset in a similar manner. When the panel is driven with left scan (Reverse scan), this offset relationship becomes inverted for even and odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed. The CXD2411AR deals with this inversion as follows. Right scan (Normal scan) Left scan (Reverse scan) H SCANNER V SCANNER Display area When using single-panel (1) When the right/left inversed-identification pin (RGT) goes L, the relationship concerning HCK output switches between odd and even lines. In this case, use HST1 for the horizontal direction start pulse. When RGT is H: Right scan mode is on. The right scan drive pulse is output by the timing generator and is supplied to the panel. When RGT is L: Left scan mode is on. The left scan drive pulse is output by the timing generator and is supplied to the panel. When using three-panels (1) In order to be able to simultaneously drive three panels, with a mixture of right/left inversion on and off, output two pulses regarding HST pulse: HST1 for right scan (Normal scan) and HST2 for left scan (Reverse scan). In addition, left and right scan outputs are necessary for the RGT signal as well. However, since this timing generator does not have an RGT (right/left inversed-identification) output pin for left scan, external measures must be taken. Similarly, external measures are also taken for HCK1 and 2. Regarding SH, the wiring of SH1 and SH4 to the driver IC. (2) When the right/left inversed-identification pin (RGT) goes L, the relationship concerning HCK output switches between odd and even lines for each output switches. When RGT is H: Right scan mode is on. The right scan (A) and left scan (B) drive pulses are output by the timing generator and are supplied to panels 1 and 2 and panel 3, respectively. When RGT is L: Left scan mode is on and (A) and (B) outputs are switched. Accordingly, panels 1 and 2 are used for left scan and panel 3 changes to right scan. - 12 - CXD2411AR Application Circuit (Three-panel LCD drive) SH1 SH2 SH3 SH4 SH1 32 SH2 33 TG SH3 34 SH4 30 SH1 SH2 SH3 SH4 Left scan driver Right scan driver Signal Driver Panel 1 TG SH1 32 SH2 33 Right scan output (A) SH3 34 SH4 30 HST1 22 Signal Driver Panel 2 (Right scan) (Right scan) SH1 32 SH2 33 Left scan output (B) SH3 34 SH4 30 HST2 14 Signal Driver Panel 3 (Left scan) HCK1 24 HCK2 23 RGT 10 VST 18 VCK1 21 VCK2 20 EN 17 CLR 16 The facing of the three panels is the same. (To all panels) RGT IN (common) - 13 - CXD2411AR SH Pulse and HCK Phase Relationship The phase relationship between the SH pulse and HCK changes according to switching between right scan (Normal scan) and left scan (Reverse scan). In the present timing, SH3 is the re-sampling pulse. RGT = H (Normal scan) RGT = L (Reverse scan) HCK1 SH1 SH2 SH3 SH4 - 14 - CXD2411AR WIDE Mode Setting the WIDE pin (Pin 4) to H, shifts the unit to WIDE mode. In this mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display. During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC and 1/2 and 1/4 for PAL, are performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the display area, black is displayed by performing high-speed scanning. The timing during high-speed scanning is a 2H cycle pulse consisting of normal drive (1H) and quadruple-speed drive (1H) and black signals are written in 28 and 27 lines, respectively of the upper and lower side of this display area. During this time, FRP is changed to a 4H cycle, HST to a 2H cycle, and EN and CLR are not output. In addition, the SBLK output, which is the black signal generation timing pulse, becomes H. (For example, black display in the panel is permitted by connecting the black signal output SBLK to the external RGB input pin of the CXA1785R/AR.) Refer to the attached sheets for detailed timing. Vertical high-speed scanning 28 LINES (28 LINES) Black display area 218 LINES (225 LINES) Display area Display area 163 LINES (169 LINES) Black display area 4 : 3 display Vertical pulse eliminator scanning (at normal-speed scanning) 16 : 9 display 27 LINES (28 LINES) Numbers in parentheses are for the LCX009AK/AKB. All other numbers are for the LCX005BK/BKB. At high-speed scanning At normal-speed scanning VCK1 Quadruple-speed scanning Normal-speed scanning HST 2H cycle FRP 4H cycle SBLK - 15 - LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7s (52fh) 4.7s (52fh) 2.1s (23fh) 2.0s (22fh) 0.5fh 1.3s (14fh) 13fh 13fh 4.5fh 4.4s (49fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 16 - EVEN FIELD 18.5fh 0.5s (6fh) 3.0s (33fh) ODD LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7s (52fh) 4.7s (52fh) 2.1s (23fh) 2.0s (22fh) 2.5fh 13fh 13fh 1.3s (14fh) 3.0fh 4.4s (49fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 17 - EVEN FIELD 18.0fh 0.5s (6fh) 3.0s (33fh) EVEN LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7s (52fh) 4.7s (52fh) 2.1s (23fh) 2.0s (22fh) 2.5fh 1.3s (14fh) 13fh 13fh 4.0fh 4.4s (49fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 18 - EVEN FIELD 18.0fh 0.5s (5fh) 3.0s (34fh) ODD LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7s (52fh) 4.7s (52fh) 2.0s (22fh) 2.0s (22fh) 0.5fh 1.4s (15fh) 13fh 13fh 5.5fh 4.5s (50fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 19 - EVEN FIELD 18.5fh 0.5s (5fh) 3.0s (34fh) EVEN LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7s (78fh) 4.7s (78fh) 2.1s (34fh) 2.0s (33fh) 0.5fh 12fh 12fh 1.3s (22fh) 2.5fh 4.4s (72fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 20 - EVEN FIELD 43.5fh 0.5s (8fh) 3.0s (50fh) ODD LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7s (78fh) 4.7s (78fh) 2.1s (34fh) 2.0s (33fh) 2.5fh 12fh 12fh 1.3s (22fh) 4.0fh 4.4s (72fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 21 - EVEN FIELD 43.0fh 0.5s (8fh) 3.0s (50fh) EVEN LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7s (78fh) 4.7s (78fh) 2.1s (34fh) 4.4s (72fh) 2.0s (33fh) 2.5fh 1.3s (22fh) 12fh 12fh 3.0fh XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 22 - EVEN FIELD 43.0fh 0.5s (7fh) 3.0s (51fh) ODD LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN CXD2411AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7s (78fh) 4.7s (78fh) 2.1s (34fh) 2.0s (33fh) 0.5fh 1.3s (22fh) 12fh 12fh 1.5fh 4.4s (72fh) XHD (BLK) HD XCLP HST1 HST2 HCK1 HCK2 - 23 - EVEN FIELD 43.5fh 0.5s (7fh) 3.0s (51fh) EVEN LINE SH1 SH2 SH3 SH4 FRP ODD FIELD VCK1 VCK2 CLR EN CXD2411AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 24 - ODD FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 25 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 - 26 - ODD FIELD FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 - 27 - EVEN FIELD FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK CXD2411AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 28 - ODD FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 29 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 30 - ODD FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 31 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB WIDE Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 32 - ODD FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB WIDE Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 33 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB WIDE Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 34 - ODD FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX005BK/BKB WIDE Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 35 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB WIDE Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 - 36 - ODD FIELD FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK CXD2411AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB WIDE Vertical Direction Timing Chart NTSC XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 37 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB WIDE Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 38 - ODD FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR LCX009AK/AKB WIDE Vertical Direction Timing Chart PAL XVD XHD CSYNC (BLK) VST VCK1 VCK2 FRP (1H inversion) - 39 - EVEN FIELD HST EN CLR FRP (1F inversion) FLD VD SBLK Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2411AR CXD2411AR AC Driving for No Signal HST1, HST2, HCK1, HCK2, FRP, VCK1, VCK2, XCLP, HD, VD, and VST are made to run free so that the LCD panel is AC driven even when there are no horizontal and vertical sync signals from the XHD and XVD pins. During this time, the PLL counter is made to run free because the horizontal sync separation circuit stops. In addition, the auxiliary V counter is used to create the reference pulse for generating VD and VST because the vertical sync separation circuit is also stopped. The cycle of this V counter is designed to be 269H for NTSC and 321H for PAL. However, when there is no vertical sync signal for 301H (NTSC) or 360H (PAL), the no signal state is assumed and the free running VD and VST pulses are generated from the next field. The RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing phase errors due to phase comparison. AFC Circuit (702/1050fh Generation) 4.7s XHD 5V RPD 2.5V 0V The center of SYNC A fully synchronized AFC circuit is built in. PLL error detection signal is generated at the following timing. The phase comparison output of the entire bottom of XHD and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter, and then it changes the varicap capacitance and the oscillating frequency is stabilized at 702, 1050fh in the LCX005BK/BKB, LCX009AK/AKB. - 40 - CXD2411AR Application Circuit AC conversion circuit (RGB driver) FRP Sample-and-hold circuit (RGB driver) Sample-and-hold circuit (RGB driver) Backlight driver circuit 36 35 34 33 32 31 30 29 28 27 26 25 RGB driver SH3 FLDO HD VSS RGB decoder N.C. XCLP SH2 SH4 SH1 +5V 37 N.C. 38 HP4 39 RPD 40 VSS 41 CKO 42 CKI 43 VDD 44 N.C. 45 XVD 46 FP1 47 FP2 48 FP3 XHD 3.3 10k 1k VD HCK1 24 HCK2 23 HST1 22 VCK1 21 VCK2 20 VDD 19 VST 18 EN 17 CLR 16 N.C. 15 LCD panel 3300p 0.01 10k 100k 20p RGB decoder L 33k 1000p SLCK PLNT XCLR WIDE SBLK TST1 TST0 TST2 RGT N.C. N.C. HST2 14 SLFR 13 LCD panel +12V 1 +5V 2 3 4 56 VSS 7 8 9 10 11 12 LCX005BK/BKB LCX009AK/AKB PAL NT 4:3 N R Reference examples of L value: when using LCX009AK/AKB when using LCX005BK/BKB 4.7H 10H Recommended varicap: 1T369 (SONY) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 41 - RGB external input (RGB driver) 16:9 +5V CXD2411AR Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 0.2 36 37 7.0 0.1 25 24 S (8.0) A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13 B (0.22) + 0.05 0.127 - 0.02 0.13 M 0.1 0.1 0.1 0.5 0.2 S (0.127) +0.05 0.127 - 0.02 (0.18) 0.18 0.03 0 to 10 0.5 0.2 DETAIL B:SOLDER DETAIL A DETAIL B:PALLADIUM NOTE: Dimension "" does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g - 42 - 0.127 0.04 + 0.08 0.18 - 0.03 |
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